Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33796
Change subject: asus/am1i-a: Fix UART 0 port while preserving the UART 1 functionality ......................................................................
asus/am1i-a: Fix UART 0 port while preserving the UART 1 functionality
It has been observed by me and Elisenda Cuadros / Gergely Kiss [1] that the boot process of this board is super slow when UART 0 is being used - even if nothing is connected to it. Fix UART 0 by initializing it at romstage.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-February/086132.html
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f --- M src/mainboard/asus/am1i-a/romstage.c 1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/33796/1
diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 4b172ea..258ca03 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -25,7 +25,8 @@ #include <superio/ite/it8623e/it8623e.h>
#define ITE_CONFIG_REG_CC 0x02 -#define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP2) +#define SERIAL_DEV1 PNP_DEV(0x2e, IT8623E_SP1) +#define SERIAL_DEV2 PNP_DEV(0x2e, IT8623E_SP2) #define GPIO_DEV PNP_DEV(0x2e, IT8623E_GPIO) #define CLKIN_DEV PNP_DEV(0x2e, IT8623E_GPIO) #define ENVC_DEV PNP_DEV(0x2e, IT8623E_EC) @@ -160,7 +161,8 @@ ite_evc_conf(ENVC_DEV);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV2, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV);
/*