Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42563 )
Change subject: [RFC] AMD APM_CNT and SMI enablement ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42563/1/src/soc/amd/picasso/southbr... File src/soc/amd/picasso/southbridge.c:
https://review.coreboot.org/c/coreboot/+/42563/1/src/soc/amd/picasso/southbr... PS1, Line 238: * ACPI tables are generated. Enable these ports indiscriminately. There is initiative CB:42377 to track failures to write to APM_CNT. Looks like the code here enables SMI's via outb(xx, APM_CNT) mechanism late in ramstage. This should possibly happen right after PARALLEL_MP or even before SMM relocation runs.
PARALLEL_MP raises SMI via lapic?