[coreboot-gerrit] [XS] Change in coreboot[main]: sb/intel/bd82x6x/pcie: Drop register write

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78238?usp=email )

Change subject: sb/intel/bd82x6x/pcie: Drop register write
......................................................................

sb/intel/bd82x6x/pcie: Drop register write

The write to register 0x42 has no effect as at this point all
of the bits are read-only. Drop the line.

Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/pcie.c
1 file changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/78238/1

diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index f5bc709..a34bc1f 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -217,10 +217,8 @@
    pci_write_config16(dev, 0x1e, reg16);

/* Enable expresscard hotplug events.  */
-	if (pci_is_hotplugable(dev)) {
+	if (pci_is_hotplugable(dev))
    	pci_or_config32(dev, 0xd8, 1 << 30);
-		pci_write_config16(dev, 0x42, 0x142);
-	}
 }

static void pch_pcie_enable(struct device *dev)