[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters

[Johnny Lin (Code Review)]

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39625 )

Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39625/2/src/soc/intel/xeon_sp/bootb... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/39625/2/src/soc/intel/xeon_sp/bootb... 
PS2, Line 34: 		.CodeRegionLength = (UINT32)CONFIG_BIOS_REGION_SIZE,
> why not hardcode to 16MiB? Thats the maximum FSP-T can support. […]

Do you mean like this?
.CodeRegionBase = (UINT32)(0x100000000ULL - 0x1000000),
.CodeRegionLength = 0x1000000,
I'll wait for others' opinion a bit.
Thanks.