build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30934 )
Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@337 PS5, Line 337: gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@338 PS5, Line 338: gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@339 PS5, Line 339: gpio_configure(GPIO(117), 2, GPIO_PULL_DOWN, GPIO_16MA, GPIO_INPUT);// CS line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@340 PS5, Line 340: gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT);// CLK line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@343 PS5, Line 343: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@344 PS5, Line 344: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@345 PS5, Line 345: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS line over 80 characters
https://review.coreboot.org/#/c/30934/5/src/soc/qualcomm/qcs405/spi.c@346 PS5, Line 346: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK line over 80 characters