[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[Julien Viard de Galbert (Code Review)]

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 14: Code-Review+1
> Patch Set 14: Code-Review-1
>
> (1 comment)
>
> One bug to fix.  The rest looks good.

Well, not really.
It should ether be PCIE_PORT2_DEV + i (as it was)
or PCIE_PORT5_DEV + i - 4 (if you really want to use PCIE_PORT5_DEV).

Best Regards