Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36339 )
Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7 ......................................................................
soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7
Set MSR 0x2e7 in any case at the end of POST to lock most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/finalize.c 5 files changed, 21 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36339/1
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 115b732..17cf4d9 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -19,8 +19,10 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> @@ -110,6 +112,9 @@
pch_finalize();
+ /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); + printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT);
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 75e7112..8c3454c 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -320,3 +320,9 @@ (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } + +/* Lock chipset memory registers to protect SMM */ +void cpu_lt_lock_memory(void) +{ + set_msr_bit(MSR_LT_LOCK_MEMORY, 0); +} diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index a70b5a1..c48449f 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -18,8 +18,10 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> @@ -109,6 +111,9 @@
pch_finalize();
+ /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); + printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT);
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 63142b9..9bf2431 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -578,11 +578,5 @@
void cpu_lock_sgx_memory(void) { - msr_t msr; - - msr = rdmsr(MSR_LT_LOCK_MEMORY); - if ((msr.lo & 1) == 0) { - msr.lo |= 1; /* Lock it */ - wrmsr(MSR_LT_LOCK_MEMORY, msr); - } + cpu_lt_lock_memory(); } diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 4cc9c83..58a8701 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -20,6 +20,7 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/cpulib.h> @@ -123,6 +124,9 @@ reg8 |= SMI_LOCK; pci_write_config8(dev, GEN_PMCON_A, reg8); } + + /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); }
static void soc_finalize(void *unused)