[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Update northbridge

[Marshall Dawson (Code Review)]

Hello Matt Papageorge, Arthur Heymans, build bot (Jenkins), Martin Roth, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34424

to look at the new patch set (#20).

Change subject: soc/amd/picasso: Update northbridge
......................................................................

soc/amd/picasso: Update northbridge

Family 17h devices are designed with a new internal architecture,
frequently referred to as the data fabric.  Although designed to
behave somewhat like the older integrated northbridge designs,
the D18Fx definitions are completely new.

Update the process of declaring memory and reserved areas to rely
on HOBs for regions above top of low memory.

AGESA sets up most of the necessary configuration
 * Immediately following FSP-S, update the northbridge routing
   registers to make the region between HPET and LAPIC as non-posted.
 * Keep enabling of VGA decode, if used, in coreboot.

Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/chip.c
M src/soc/amd/picasso/include/soc/northbridge.h
M src/soc/amd/picasso/include/soc/pci_devs.h
M src/soc/amd/picasso/northbridge.c
4 files changed, 183 insertions(+), 281 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34424/20