Attention is currently required from: Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl. Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61341 )
Change subject: [UNTESTED] mb/intel/harcuvar: Fix memory-down code ......................................................................
Patch Set 1: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61341/comment/43a09014_0f56048a PS1, Line 10: read the maybe: ... get memory mapped location of ...
Patchset:
PS1: looks ok, thx Angel for providing code update. Just a note: Harcuvar CRB have DIMM memory slots and uses standard modules with SPD data by default. Provided code is just an example how to use feature on memory down platforms or when we want to use coreboot provided SPD data instead of module built in SPD content. I`ve used previous example code on Harcuvar CRB to test FSP-M behavior on different SPD data without need to physically replace memory modules.
File src/mainboard/intel/harcuvar/romstage.c:
https://review.coreboot.org/c/coreboot/+/61341/comment/c6359dc6_755ba8ed PS1, Line 109: Channel 0 is memory down and channel 1 Channel 0 DIMM 0 .....channel 1 DIMM 0