[coreboot-gerrit] Patch set updated for coreboot: ea43d74 baytrail: set max frequency early in romstage

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4869

-gerrit

commit ea43d74fc24edc00a0151ea7201a00fc59fce879
Author: Aaron Durbin 
Date:   Mon Oct 7 17:12:20 2013 -0500

baytrail: set max frequency early in romstage

Set the BSP to operate at max frequency early in romstage.
    The call to punit_init() is when the frequency actually ramps as
    that makes the punit actually start working.

BUG=chrome-os-partner:22857
    BRANCH=None
    TEST=Built and booted. Noted operating frequency status is max.

Change-Id: Icfd9e5c7682aa21fc740bd687607ca6a66597d5e
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://chromium-review.googlesource.com/172131
    Reviewed-by: Duncan Laurie 
---
 src/soc/intel/baytrail/baytrail/ramstage.h |  1 +
 src/soc/intel/baytrail/baytrail/romstage.h |  1 +
 src/soc/intel/baytrail/romstage/romstage.c |  2 ++
 src/soc/intel/baytrail/tsc_freq.c          | 29 +++++++++++++++++++++++++++++
 4 files changed, 33 insertions(+)

diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h
index d1fe0f1..ff0397c 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/baytrail/ramstage.h
@@ -25,6 +25,7 @@
 /* The baytrail_init_pre_device() function is called prior to device
  * initialization, but it's after console and cbmem has been reinitialized. */
 void baytrail_init_pre_device(void);
+void set_max_freq(void);

extern struct pci_operations soc_pci_ops;

diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h
index 4918a02..43c60ec 100644
--- a/src/soc/intel/baytrail/baytrail/romstage.h
+++ b/src/soc/intel/baytrail/baytrail/romstage.h
@@ -49,6 +49,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state);
 void gfx_init(void);
 void tco_disable(void);
 void punit_init(void);
+void set_max_freq(void);

#if CONFIG_ENABLE_BUILTIN_COM1
 void byt_config_com1_and_enable(void);
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 6e965bc..0035019 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -126,6 +126,8 @@ void romstage_common(struct romstage_params *params)

console_init();

+	set_max_freq();
+
    punit_init();

gfx_init();
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c
index e0b2b7e..0cf7273 100644
--- a/src/soc/intel/baytrail/tsc_freq.c
+++ b/src/soc/intel/baytrail/tsc_freq.c
@@ -21,6 +21,12 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
 #include <baytrail/msr.h>
+#if !defined(__PRE_RAM__)
+#include <baytrail/ramstage.h>
+#else
+#include <baytrail/romstage.h>
+#endif
+

#define BCLK 100 /* 100 MHz */
 unsigned long tsc_freq_mhz(void)
@@ -30,3 +36,26 @@ unsigned long tsc_freq_mhz(void)
    platform_info = rdmsr(MSR_PLATFORM_INFO);
    return BCLK * ((platform_info.lo >> 8) & 0xff);
 }
+
+void set_max_freq(void)
+{
+	msr_t perf_ctl;
+	msr_t msr;
+
+	/* Enable speed step. */
+	msr = rdmsr(MSR_IA32_MISC_ENABLES);
+	msr.lo |= (1 << 16);
+	wrmsr(MSR_IA32_MISC_ENABLES, msr);
+
+	/* Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
+	* the PERF_CTL. */
+	msr = rdmsr(MSR_IACORE_RATIOS);
+	perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
+	/* Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
+	* the PERF_CTL. */
+	msr = rdmsr(MSR_IACORE_VIDS);
+	perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
+	perf_ctl.hi = 0;
+
+	wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
+}