Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32025 )
Change subject: mb/roda/rk9: Document flash header ......................................................................
mb/roda/rk9: Document flash header
Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M Documentation/mainboard/index.md A Documentation/mainboard/roda/rk9/flash_header.md 2 files changed, 27 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 7e0dab2..fb4f502 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -81,6 +81,10 @@
- [MS-7707](msi/ms7707/ms7707.md)
+## Roda + +- [RK9 Flash Header](roda/rk9/flash_header.md) + ## SiFive
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) diff --git a/Documentation/mainboard/roda/rk9/flash_header.md b/Documentation/mainboard/roda/rk9/flash_header.md new file mode 100644 index 0000000..c2978cb --- /dev/null +++ b/Documentation/mainboard/roda/rk9/flash_header.md @@ -0,0 +1,23 @@ +Roda RK9 Flash Header +===================== + +There is a 5x2 pin, 1.27mm pitch header *J1* south of the BIOS flash. It +follows the pinout of the Dediprog adaptor board: + + +------+ + | 1 2 | 1: HOLD 2 2: CS 2 + | 3 4 | 3: CS 1 4: VCC + | 5 6 | 5: MISO 6: HOLD 1 + | 7 8 | 7: 8: CLK + | 9 10 | 9: GND 10: MOSI + +------+ + +Pins 3 to 10 directly map to the regular SPI flash pinout. + +There is also a *JP17* around. Ideally, it should be closed during +programming (isolates the SPI bus from the southbridge): + + +---+ + | 1 | 1: SF100-I/O3 + | 2 | 2: GND + +---+