[coreboot-gerrit] [M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 5:

(1 comment)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/fb5b1fbc_cb2a6c8b?usp... :
PS2, Line 77: {7, 34, 20, -1}
> Hmm, supposedly the ASM1061 worked in the original P8Z77-V port

Wow, all these went under my nose unnoticed! And to think that I should have a bit of an idea what PP and OD means individually, and Bill's vendor log (which I saved) did show that PP/OD register set as 0x8c.

I just pushed an update with the fix Let's see how it works for Bill.

(To think of it, before this update PCIEX16_3 at 4x probably would not work even with straps set, if Bill were to try.)