Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38288 )
Change subject: soc/intel/cannonlake: Add Iccmax and loadlines for CML-S ......................................................................
soc/intel/cannonlake: Add Iccmax and loadlines for CML-S
This patch adds Iccmax and AC/DC loadlines for CML-S CPUs. The information is from CML EDS volume 1, doc #606599.
Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72 Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 92 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38288/1
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 7096b62..78f51bc 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -91,37 +91,53 @@ /* * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. + * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML. * * Platform Segment SA IA GT (GT/GTx) - * --------------------------------------------------------------------- - * CFL-U (28W) GT3 quad 8.5 64 64 - * CFL-U (28W) GT3 dual 8.5 64 64 + * ---------------------------------------------------------------------- + * CFL-U (28W) GT3 quad 8.5 64 64 + * CFL-U (28W) GT3 dual 8.5 64 64 * - * CFL-H (45W) GT2 hex 11.1 128 0 - * CFL-H (45W) GT2 quad 11.1 86 0 + * CFL-H (45W) GT2 hex 11.1 128 0 + * CFL-H (45W) GT2 quad 11.1 86 0 * - * CFL-S (95W) GT2 octa 11.1 193 45 + * CFL-S (95W) GT2 octa 11.1 193 45 * - * CFL-S (95W) GT2 hex 11.1 138 45 - * CFL-S (65W) GT2 hex 11.1 133 45 - * CFL-S (80W) GT2 hex 11.1 133 45 - * CFL-S (35W) GT2 hex 11.1 104 35 + * CFL-S (95W) GT2 hex 11.1 138 45 + * CFL-S (65W) GT2 hex 11.1 133 45 + * CFL-S (80W) GT2 hex 11.1 133 45 + * CFL-S (35W) GT2 hex 11.1 104 35 * - * CFL-S (91W) GT2 quad 11.1 100 45 - * CFL-S (83W) GT2 quad 11.1 100 45 - * CFL-S (71W) GT2 quad 11.1 100 45 - * CFL-S (65W) GT2 quad 11.1 79 45 - * CFL-S (62W) GT2 quad 11.1 79 45 - * CFL-S (35W) GT2 quad 11.1 66 35 + * CFL-S (91W) GT2 quad 11.1 100 45 + * CFL-S (83W) GT2 quad 11.1 100 45 + * CFL-S (71W) GT2 quad 11.1 100 45 + * CFL-S (65W) GT2 quad 11.1 79 45 + * CFL-S (62W) GT2 quad 11.1 79 45 + * CFL-S (35W) GT2 quad 11.1 66 35 * - * CFL-S (58W) GT2 dual 11.1 79 45 - * CFL-S (54W) GT2 dual 11.1 58 45 - * CFL-S (35W) GT2 dual 11.1 40 35 + * CFL-S (58W) GT2 dual 11.1 79 45 + * CFL-S (54W) GT2 dual 11.1 58 45 + * CFL-S (35W) GT2 dual 11.1 40 35 * - * CNL-U (15W) 13 34 0 + * CNL-U (15W) 13 34 0 * - * WHL-U (15W) GT2 quad 6 70 31 - * WHL-U (15W) GT2 dual 6 35 31 + * WHL-U (15W) GT2 quad 6 70 31 + * WHL-U (15W) GT2 dual 6 35 31 + * + * CML-S 10-Core (125W) GT2/0 11.1 245 35 + * CML-S 10-Core (65W) GT2/0 11.1 210 35 + * CML-S 10-Core (80W) GT2 11.1 210 35 + * CML-S 10-Core (35W) GT2 11.1 140 35 + * CML-S 8-Core (125W) GT2/0 11.1 245 35 + * CML-S 8-Core (65W) GT2/0 11.1 210 35 + * CML-S 8-Core (80W) GT2 11.1 210 35 + * CML-S 8-Core (35W) GT2 11.1 140 35 + * CML-S 6-Core (125/65/80W) 11.1 140 35 + * CML-S 6-Core (35W) GT2/0 11.1 104 35 + * CML-S 4-Core (65W) GT2 11.1 102 35 + * CML-S 4-Core (35W) GT2 11.1 65 35 + * CML-S 2-Core (58W) GT2/1 11.1 60 35 + * CML-S 2-Core (35W) GT2/1 11.1 55 35 * * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. */ @@ -215,6 +231,39 @@
return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35); + if (tdp > 35) { + if (tdp >= 125) + icc_max[VR_IA_CORE] = VR_CFG_AMP(245); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + } + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); + if (tdp > 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_4: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 65, 35, 35); + if (tdp > 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(102); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 35, 35); + if (tdp > 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(60); + + return icc_max[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } @@ -273,6 +322,27 @@ VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1); return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + const uint16_t tdp = cpu_get_power_max(); + if (tdp > 35) + loadline[VR_IA_CORE] = 1.1; + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + const uint16_t tdp = cpu_get_power_max(); + if (tdp >= 125) + loadline[VR_IA_CORE] = 1.1; + + return loadline[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); }