Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31055
Change subject: soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery ......................................................................
soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery
Disabling CpuRatio UPD for FSP will ensure it does not force a hard reset to set the CPU Flex Ratio at boot. This is important in a recovery mode boot where the SOC will lose power and need to set the flex ratio again.
Disabling SaGv makes recovery mode training faster and mirrors the setting that was done on Skylake.
BUG=b:123305400 TEST=reliably enter recovery mode on sarien
Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31055/1
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 91810e8..ed7ece5 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -20,6 +20,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <vendorcode/google/chromeos/chromeos.h>
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { @@ -54,6 +55,13 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + + /* Disable CPU Flex Ratio and SaGv in recovery mode */ + if (vboot_recovery_mode_enabled()) { + m_cfg->CpuRatio = 0; + m_cfg->SaGv = 0; + } + /* If ISH is enabled, enable ISH elements */ if (!dev) m_cfg->PchIshEnable = 0;