[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Cache the TSEG region

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35026 )

Change subject: soc/intel/{cnl, icl}: Cache the TSEG region
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Patch Set 4:
> Patch Set 2:
>
> Can we get the cbmem -t numbers of commit 3b7091, with the change of using either WC of WP for both CBMEM and TSEG.
>
> I still think there is something wrong wrt. disabling non-evict mode on the platform, behaviour of  timestamp 1100 is just weird.

please refer to https://review.coreboot.org/c/coreboot/+/34995/7 commit msg, i have captured boot time data across different MTRR type