Krzysztof M Sywula has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32026
Change subject: soc/intel/cannonlake: FSP UPD update ......................................................................
soc/intel/cannonlake: FSP UPD update
Exposed FSP params: SlpS0WithGbeSupport, PchPmSlpS0VmRuntimeControl, PchPmSlpS0VmRuntimeControl, PchPmSlpS0VmRuntimeControl. Their values can be controled from devicetree.cb.
Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e Signed-off-by: Krzysztof Sywula krzysztof.m.sywula@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32026/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b4d78f3..72fb45a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -138,6 +138,12 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8];
+ /* Power management related */ + uint8_t SlpS0WithGbeSupport; + uint8_t PchPmSlpS0VmRuntimeControl; + uint8_t PchPmSlpS0Vm070VSupport; + uint8_t PchPmSlpS0Vm075VSupport; + /* Audio related */ uint8_t PchHdaDspEnable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 77d82d6..58dab3f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -164,6 +164,12 @@ else params->PchLanEnable = dev->enabled;
+ /* Power management related */ + params->SlpS0WithGbeSupport = config->SlpS0WithGbeSupport; + params->PchPmSlpS0VmRuntimeControl = config->PchPmSlpS0VmRuntimeControl; + params->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport; + params->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport; + /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;