16 Jan
2020
16 Jan
'20
12:50 p.m.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38432 )
Change subject: soc/intel/cannonlake: Add chip config for SATA strength ......................................................................
Patch Set 2: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e
Gerrit-Change-Number: 38432
Gerrit-PatchSet: 2
Gerrit-Owner: Jamie Chen jamie.chen@intel.com
Gerrit-Reviewer: Edward O'Callaghan quasisec@chromium.org
Gerrit-Reviewer: Jamie Chen jamie.chen@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Thu, 16 Jan 2020 11:50:13 +0000
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