Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41049 )
Change subject: nb/intel/i440bx: Refactor ACPI code ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41049/3/src/northbridge/intel/i440b... File src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl:
https://review.coreboot.org/c/coreboot/+/41049/3/src/northbridge/intel/i440b... PS3, Line 62: ShiftLeft(0x10000000, 4, Local0)
*poke*
I actually have concerns after checking the disassembly.
With both ASL 1 and ASL 2 syntax, iasl optimizes this line to: Local0 = 0x0000000100000000
A thoroughly 64-bit value. From previous notes we used bit shifts here so the math would work with both 32 and 64 bits.
I want to validate the actual results returned to Linux ACPI system before fixing this one.