[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Clear PMCON status bits

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32503 )

Change subject: soc/intel/icelake: Clear PMCON status bits
......................................................................

soc/intel/icelake: Clear PMCON status bits

This patch ports CB:31902 changes from CNL to ICL.

The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.

Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503
Reviewed-by: Rizwan Qureshi 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/icelake/finalize.c
M src/soc/intel/icelake/include/soc/pm.h
M src/soc/intel/icelake/pmutil.c
3 files changed, 19 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Rizwan Qureshi: Looks good to me, approved

diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c
index c1e6dd0..e061cda 100644
--- a/src/soc/intel/icelake/finalize.c
+++ b/src/soc/intel/icelake/finalize.c
@@ -87,6 +87,8 @@
    }

pch_handle_sideband(config);
+
+	pmc_clear_pmcon_sts();
 }

static void soc_finalize(void *unused)
diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h
index 9caf49f..44888ec 100644
--- a/src/soc/intel/icelake/include/soc/pm.h
+++ b/src/soc/intel/icelake/include/soc/pm.h
@@ -168,5 +168,8 @@
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);

+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
 #endif /* !defined(__ACPI__) */
 #endif
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 96ff52d..e1b1665 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -141,6 +141,20 @@
    write8(addr, disb_val);
 }

+void pmc_clear_pmcon_sts(void)
+{
+	uint32_t reg_val;
+	uint8_t *addr;
+	addr = pmc_mmio_regs();
+
+	reg_val = read32(addr + GEN_PMCON_A);
+	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+	 * while retaining MS4V write-1-to-clear bit */
+	reg_val &= ~(MS4V);
+
+	write32((addr + GEN_PMCON_A), reg_val);
+}
+
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE