Hello Po Xu,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46390
to review the following change.
Change subject: soc/mediatek/mt8192: Add auxadc driver ......................................................................
soc/mediatek/mt8192: Add auxadc driver
Add MT8192 auxadc driver.
Signed-off-by: Po Xu jg_poxu@mediatek.com Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/auxadc.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/auxadc.h A src/soc/mediatek/mt8192/include/soc/efuse.h 5 files changed, 116 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46390/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d417ae2..9bb9cfd 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y)
+bootblock-y += auxadc.c bootblock-y += bootblock.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c @@ -13,12 +14,14 @@ bootblock-y += mt6315.c bootblock-y += mt6359p.c
+verstage-y += auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c
+romstage-y += auxadc.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += flash_controller.c @@ -29,6 +32,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c
+ramstage-y += auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c diff --git a/src/soc/mediatek/mt8192/auxadc.c b/src/soc/mediatek/mt8192/auxadc.c new file mode 100755 index 0000000..3f9238b --- /dev/null +++ b/src/soc/mediatek/mt8192/auxadc.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <assert.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/auxadc.h> +#include <soc/efuse.h> +#include <soc/infracfg.h> +#include <timer.h> + +static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE; + +#define ADC_GE_A_SHIFT 10 +#define ADC_GE_A_MASK (0x3ff << ADC_GE_A_SHIFT) +#define ADC_OE_A_SHIFT 0 +#define ADC_OE_A_MASK (0x3ff << ADC_OE_A_SHIFT) +#define ADC_CALI_EN_A_SHIFT 20 +#define ADC_CALI_EN_A_MASK (0x1 << ADC_CALI_EN_A_SHIFT) + +static int cali_oe; +static int cali_ge; +static int calibrated = 0; +static void mt_auxadc_update_cali(void) +{ + uint32_t cali_reg; + int cali_ge_a; + int cali_oe_a; + + cali_reg = read32(&mtk_efuse->adc_cali_reg); + + if ((cali_reg & ADC_CALI_EN_A_MASK) != 0) { + cali_oe_a = (cali_reg & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT; + cali_ge_a = (cali_reg & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT; + cali_ge = cali_ge_a - 512; + cali_oe = cali_oe_a - 512; + } +} +static uint32_t auxadc_get_rawdata(int channel) +{ + setbits32(&mt8192_infracfg->module_sw_cg_1_clr, 1 << 10); + assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1))); + + clrbits32(&mtk_auxadc->con1, 1 << channel); + assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12)))); + + setbits32(&mtk_auxadc->con1, 1 << channel); + udelay(25); + assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12))); + + uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF; + + setbits32(&mt8192_infracfg->module_sw_cg_1_set, 1 << 10); + + return value; +} + +int auxadc_get_voltage(unsigned int channel) +{ + uint32_t raw_value; + assert(channel < 16); + + if (!calibrated) { + mt_auxadc_update_cali(); + calibrated = 1; + } + + /* 1.5V in 4096 steps */ + raw_value = auxadc_get_rawdata(channel); + raw_value = raw_value - cali_oe; + return (int)((int64_t)raw_value * 1500000 / (4096 + cali_ge)); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h old mode 100644 new mode 100755 index e9cb788..9760c88 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -26,6 +26,7 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, @@ -37,6 +38,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, diff --git a/src/soc/mediatek/mt8192/include/soc/auxadc.h b/src/soc/mediatek/mt8192/include/soc/auxadc.h new file mode 100755 index 0000000..18350d6 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/auxadc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_ADC_H +#define _MTK_ADC_H + +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +/* Return voltage in uVolt */ +int auxadc_get_voltage(unsigned int channel); +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/efuse.h b/src/soc/mediatek/mt8192/include/soc/efuse.h new file mode 100755 index 0000000..f0f3405 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_EFUSE_H +#define _MTK_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t rserved[109]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x1b4); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif