[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Cache the TSEG region

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35026 )

Change subject: soc/intel/{cnl, icl}: Cache the TSEG region
......................................................................

soc/intel/{cnl, icl}: Cache the TSEG region

This patch helps to save additional ~19ms of booting time in
normal boot and s3 resume on CML-hatch.

BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot

Without this CL:
Total Time: 929ms

With this CL: (TSEG marked as WB)
Total Time: 910ms

For test marked TSEG as WP/WC:
Total Time: ~920ms

Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Kyösti Mälkki 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/icelake/memmap.c
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  Aaron Durbin: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index f0c21d9..f3286cc 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -280,4 +280,7 @@
    printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
    top_of_ram -= 16*MiB;
    postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+	/* Cache the TSEG region */
+	postcar_enable_tseg_cache(pcf);
 }
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 71368c6..20c4e6f 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -278,4 +278,7 @@
    printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
    top_of_ram -= 16*MiB;
    postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+	/* Cache the TSEG region */
+	postcar_enable_tseg_cache(pcf);
 }