[coreboot-gerrit] Change in coreboot[master]: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for...

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35313 )

Change subject: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports
......................................................................

src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports

Currently it is impossible to enable ACS with AGESA by setting the correct
bit for AmdInitMid phase. AGESA code path does not call the right function
that enables these functionalities. Disabled ACS result in multiple PCIe
devices to be assigned to the same IOMMU group. Without IOMMU group
separation the devices cannot be passed through independently.

Enable Access Control Services and Advanced Error Reporting for PCI Express
bridges in order to have PCIe devices in separate IOMMU groups for correct
passthrough.

TEST=run dmesg on Debian Buster and check whether PCIe devices have separate
groups

Signed-off-by: Michał Żygowski 
Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15
---
M src/northbridge/amd/pi/00730F01/northbridge.c
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35313/1

diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index ba17c61..fede1e9 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -783,6 +783,25 @@
    pci_write_config32(dev, 0xF8, 0);
    pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */

+	/* Select GPP link core IO Link Strap Control register 0xB0 */
+	pci_write_config32(dev, 0xE0, 0x014000B0);
+	value = pci_read_config32(dev, 0xE4);
+
+	/* Enable AER (bit 5) and ACS (bit 6 undocumented) */
+	value |= (BIT(5) | BIT(6));
+	pci_write_config32(dev, 0xE4, value);
+
+	/* Select GPP link core Wrapper register 0x00 (undocumented) */
+	pci_write_config32(dev, 0xE0, 0x01300000);
+	value = pci_read_config32(dev, 0xE4);
+
+	/* Enable ACS capabilities straps including sub-items. From lspci it
+	 * looks like these bits enable: Source Validation and Translation
+	 * Blocking
+	 */
+	value |= (BIT(24) | BIT(25) | BIT(26));
+	pci_write_config32(dev, 0xE4, value);
+
    /* disable No Snoop */
    dev = pcidev_on_root(1, 1);
    if (dev != NULL) {