[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Reset DQS probe on all channels

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49385 )

Change subject: nb/intel/x4x: Reset DQS probe on all channels
......................................................................

nb/intel/x4x: Reset DQS probe on all channels

Eaglelake MRC 2.55 does this, and also stalls for less time.

Change-Id: Iaaefd32c341a490e5c129df865407ec3f8da8212
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49385
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/rcven.c
1 file changed, 7 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 8a86ce9..1f49beb 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -28,11 +28,13 @@
 {
    u32 sample_offset = 0x400 * channel + 0x561 + lane * 4;

-	/* Reset the DQS probe */
-	MCHBAR8(RESET_CNTL(channel)) &= ~0x2;
-	udelay(2);
-	MCHBAR8(RESET_CNTL(channel)) |= 0x2;
-	udelay(2);
+	/* Reset the DQS probe, on both channels? */
+	for (u8 i = 0; i < TOTAL_CHANNELS; i++) {
+		MCHBAR8(RESET_CNTL(i)) &= ~0x2;
+		udelay(1);
+		MCHBAR8(RESET_CNTL(i)) |= 0x2;
+		udelay(1);
+	}
    mfence();
    /* Read strobe */
    read32((u32 *)addr);