Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85826?usp=email )
Change subject: mb/google/nissa/var/telith: Configure Acoustic noise mitigation ......................................................................
mb/google/nissa/var/telith: Configure Acoustic noise mitigation
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:387056119 BRANCH=none TEST=built firmware and verified by power team, and noise pass.
Change-Id: I11e1fae6d0b8508760090956ca6d77b012aa4bad Signed-off-by: Kun Liu liukun11@huaqin.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85826 Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: Eric Lai ericllai@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Rui Zhou zhourui@huaqin.corp-partner.google.com Reviewed-by: Kapil Porwal kapilporwal@google.com --- M src/mainboard/google/brya/variants/telith/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-)
Approvals: Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Rui Zhou: Looks good to me, but someone else must approve build bot (Jenkins): Verified Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb index 964d49c..cac770f 100644 --- a/src/mainboard/google/brya/variants/telith/overridetree.cb +++ b/src/mainboard/google/brya/variants/telith/overridetree.cb @@ -20,6 +20,13 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled"
+ # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + # EMMC Tx CMD Delay # Refer to EDS-Vol2-42.3.7. # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.