[coreboot-gerrit] [XS] Change in coreboot[main]: sb/intel/bd82x6x: Warn about slow PCIe downstream devices

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78229?usp=email )

Change subject: sb/intel/bd82x6x: Warn about slow PCIe downstream devices
......................................................................

sb/intel/bd82x6x: Warn about slow PCIe downstream devices

Warn when a device took longer than usual to appear.
Use the PDS bit to detect if a root port has a downstream
device connected and warn if enumeration failed.

Test: On Lenovo X220 all PCIe device are visible, thus the
      added code path is never taken.

Change-Id: I86b498b89d672b239d9951e116dc3680030666a6
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/pcie.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/78229/1

diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 59ef2cb..f1817ba 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -234,6 +234,10 @@
    	/* Normal PCIe Scan */
    	pciexp_scan_bridge(dev);
    }
+	if ((pci_read_config32(dev, D28Fx_SLSTS) & PDS) &&
+	    !dev_is_active_bridge(dev))
+		printk(BIOS_WARNING, "%s: Has a slow downstream device. Enumeration failed.\n",
+			dev_path(dev));

/* Late Power Management init after bridge device enumeration */
    pch_pcie_pm_late(dev);