[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Patrick Rudolph.
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37190

to look at the new patch set (#8).

Change subject: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR
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soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR

This adds a macro to find an available MTRR(s) to set up CAR.
This added complexity is not required on bootpaths without bootguard
but with bootguard MTRR's have already been set up by the ACM so
we need to figure out at runtime which ones are available.

Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 44 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37190/8