Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43308 )
Change subject: soc/amd/picasso: Init SPI speeds & mode in psp_verstage ......................................................................
soc/amd/picasso: Init SPI speeds & mode in psp_verstage
To make the SPI ROM reads as fast as possible for verstage verification, we need to set up the SPI bus to read at the speeds we're using in the rest of coreboot.
BUG=b:159811539 TEST=Build & boot. Verify that boot time decreases & that verstage still passes.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc --- M src/soc/amd/picasso/psp_verstage/fch.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43308/1
diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 9059c9e..16c9ca9 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -4,6 +4,7 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> +#include <amdblocks/spi.h> #include <arch/exception.h> #include <arch/hlt.h> #include <arch/io.h> @@ -79,6 +80,7 @@ {"eSPI", {FCH_IO_DEVICE_ESPI}, espi_set_bar}, {"I2C2", {FCH_IO_DEVICE_I2C, 2}, i2c2_set_bar}, {"I2C3", {FCH_IO_DEVICE_I2C, 3}, i2c3_set_bar}, + {"SPI", {FCH_IO_DEVICE_SPI}, spi_set_base}, };
uintptr_t *map_spi_rom(void) @@ -156,4 +158,5 @@ espi_setup(); espi_configure_decodes(); } + fch_spi_config_modes(); }