[coreboot-gerrit] [S] Change in coreboot[main]: vendorcode/amd/fsp/glinda: Update usb_phy_config structure

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84435?usp=email )

Change subject: vendorcode/amd/fsp/glinda: Update usb_phy_config structure
......................................................................

vendorcode/amd/fsp/glinda: Update usb_phy_config structure

Updates the structures to match the ones in the FSP.

Signed-off-by: Maximilian Brune 
Change-Id: I0603f5da689b6738ea54305a665b150121bc520c
Original-signed-off-by: Satya SreenivasL 
Original-reviewed-by: Anand Vaikar 
Original-reviewed-by: Ritul Guru 
Original-tested-by: Satya Sreenivas L 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84435
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/mainboard/amd/birman/devicetree_glinda.cb
M src/mainboard/amd/birman_plus/devicetree_glinda.cb
M src/vendorcode/amd/fsp/glinda/FspUsb.h
3 files changed, 5 insertions(+), 13 deletions(-)

Approvals:
  Felix Held: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb
index 2e06f2b..cae73aa 100644
--- a/src/mainboard/amd/birman/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman/devicetree_glinda.cb
@@ -147,8 +147,6 @@
    	},
    	.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
    	.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
-		.BatteryChargerEnable = 0,
-		.PhyP3CpmP4Support = 0,
    }"

register "gpp_clk_config[0]" = "GPP_CLK_REQ"
diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
index e867f01..9e2f4b3 100644
--- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
@@ -147,8 +147,6 @@
    	},
    	.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
    	.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
-		.BatteryChargerEnable = 0,
-		.PhyP3CpmP4Support = 0,
    }"

register "gpp_clk_config[0]" = "GPP_CLK_REQ"
diff --git a/src/vendorcode/amd/fsp/glinda/FspUsb.h b/src/vendorcode/amd/fsp/glinda/FspUsb.h
index c2132eb..ca0a16b 100644
--- a/src/vendorcode/amd/fsp/glinda/FspUsb.h
+++ b/src/vendorcode/amd/fsp/glinda/FspUsb.h
@@ -1,16 +1,14 @@
 #ifndef __FSPUSB_H__
 #define __FSPUSB_H__

-/* TODO: Update for Glinda */
-
 #include <FspUpd.h>

-#define FSP_USB_STRUCT_MAJOR_VERSION	0xd
-#define FSP_USB_STRUCT_MINOR_VERSION	0xe
+#define FSP_USB_STRUCT_MAJOR_VERSION	0xf
+#define FSP_USB_STRUCT_MINOR_VERSION	0x2

-#define USB2_PORT_COUNT 6
+#define USB2_PORT_COUNT 8
 #define USB3_PORT_COUNT 3
-#define USBC_COMBO_PHY_COUNT 2
+#define USBC_COMBO_PHY_COUNT 3

struct fch_usb2_phy {
    uint8_t compdistune;		///< COMPDISTUNE
@@ -55,10 +53,8 @@
    uint8_t			Reserved0;
    struct fch_usb2_phy	Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
    struct fch_usb3_phy	Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
-	uint8_t			BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
-	uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
    uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
-	uint8_t			Reserved2[4];
+	uint8_t			Reserved1[5];
 } __packed;

#endif