[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/xeon_sp: Override cache error correction type and cache...

[Morgan Jang (Code Review)]

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46119 )

Change subject: src/soc/intel/xeon_sp: Override cache error correction type and cache sram type in SMBIOS type 7
......................................................................

src/soc/intel/xeon_sp: Override cache error correction type and cache sram type in SMBIOS type 7

TEST=Execute "dmidecode -t 7" to check if cache error correction type and
cache sram type is correct for each cache level

Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d
Signed-off-by: Morgan Jang 
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/ramstage.c
2 files changed, 14 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46119/1

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 3bbf6b7..40dafb5 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -7,7 +7,7 @@

bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
 romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
-ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c
+ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c ramstage.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
 postcar-y += spi.c

diff --git a/src/soc/intel/xeon_sp/ramstage.c b/src/soc/intel/xeon_sp/ramstage.c
new file mode 100644
index 0000000..d4334da
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <smbios.h>
+
+unsigned int smbios_cache_error_correction_type(void)
+{
+	return SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT;
+}
+
+unsigned int smbios_cache_sram_type(void)
+{
+	return SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS;
+}