Xiang W has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53944 )
Change subject: arch/riscv: Add SMP support for exception handling ......................................................................
arch/riscv: Add SMP support for exception handling
The previous exception handling code does not support SMP. If start Linux directly through coreboot, it will be a big problem.
Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b Signed-off-by: Xiang W wxjstz@12.com --- M src/arch/riscv/bootblock.S M src/arch/riscv/ramstage.S M src/arch/riscv/trap_util.S 3 files changed, 17 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/53944/1
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 12fda32..e21047c 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -36,15 +36,16 @@ STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 + # mscratch points to the entry of the exception stack + li t1, RISCV_PGSIZE / 2 - MENTRY_FRAME_SIZE + add t1, t1, t0 + csrw mscratch, t1
# initialize hart-local storage csrr a0, mhartid csrrw a1, mscratch, zero call hls_init
- li a0, CONFIG_RISCV_WORKING_HARTID - call smp_pause - # initialize entry of interrupt/exception la t0, trap_entry csrw mtvec, t0 @@ -54,6 +55,10 @@
# set up the mstatus register call mstatus_init + + li a0, CONFIG_RISCV_WORKING_HARTID + call smp_pause + tail main
// These codes need to be implemented on a specific SoC. diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 921c46d..df5ce68 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -25,14 +25,15 @@ STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 + # mscratch points to the entry of the exception stack + li t1, RISCV_PGSIZE / 2 - MENTRY_FRAME_SIZE + add t1, t1, t0 + csrw mscratch, t1
# initialize hart-local storage csrr a0, mhartid call hls_init
- li a0, CONFIG_RISCV_WORKING_HARTID - call smp_pause - # initialize entry of interrupt/exception la t0, trap_entry csrw mtvec, t0 @@ -43,6 +44,10 @@ call exit_car # set up the mstatus register call mstatus_init + + li a0, CONFIG_RISCV_WORKING_HARTID + call smp_pause + tail main
# These codes need to be implemented on a specific SoC diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index f1c4c4d..88ad6d5 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -100,25 +100,7 @@ .global trap_entry .align 2 # four byte alignment, as required by mtvec trap_entry: - csrw mscratch, sp - - # SMP isn't supported yet, to avoid overwriting the same stack with different - # harts that handle traps at the same time. - # someday this gets fixed. - //csrr sp, mhartid - csrr sp, 0xf14 -.Lsmp_hang: - bnez sp, .Lsmp_hang - - # Use a different stack than in the main context, to to avoid overwriting - # stack data. - # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if - # the previous mode was M, because it would be a very bad idea to use a stack - # pointer provided by unprivileged code! - la sp, _estack - addi sp, sp, -2048 # 2 KiB is half of the stack space - addi sp, sp, -MENTRY_FRAME_SIZE - + csrrw sp, mscratch, sp save_tf move a0,sp jal trap_handler