Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58694 )
Change subject: mb/google/brya/var/redrix: Disable autonomous GPIO power management ......................................................................
mb/google/brya/var/redrix: Disable autonomous GPIO power management
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully.
BUG=b:202246591 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage.
Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49 Signed-off-by: Wisley Chen wisley.chen@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 10 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 878fd56..67cb7f3 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -31,8 +31,17 @@ end end chip soc/intel/alderlake + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" - register "CnviBtAudioOffload" = "true" # FIVR RFI Spread Spectrum 6% register "FivrSpreadSpectrum" = "FIVR_SS_6"