[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x/raminit: Fix Clock Enable on DDR3

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50353 )

Change subject: nb/intel/x4x/raminit: Fix Clock Enable on DDR3
......................................................................

nb/intel/x4x/raminit: Fix Clock Enable on DDR3

On Asus P5QC this allows raminit to progress further (there are still
other issues).

Add a comment why the code differs from the reference code (or what
the blob on Intel boards does).

Change-Id: Ie1eb77ed2d2b563fb3b92ca33b900f7d1dbc85fe
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit_ddr23.c
1 file changed, 9 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/50353/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index fc39a5d..ad17514 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -771,10 +771,15 @@
    			(u32)(reg8 << 24));

} else { /* DDR3 */
-			FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
-				MCHBAR8_AND(0x400 * i + 0x5a0 + 3,
-					~rank2clken[r + i * 4]);
-			}
+			/*
+			 * On some boards this does not seem to work, so enable the
+			 * clock for all ranks.
+			 * 	FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
+			 *		MCHBAR8_AND(0x400 * i + 0x5a0 + 3,
+			 *			~rank2clken[r + i * 4]);
+			 *	}
+			 */
+			MCHBAR8_AND(0x400 * i + 0x5a0 + 3, 0);
    	}

//reg8 = 0x00; // FIXME don't switch on all clocks anyway