Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56205 )
Change subject: mb/siemens/chili: Drop ineffective `SaGv` setting ......................................................................
mb/siemens/chili: Drop ineffective `SaGv` setting
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it does not use ULT/ULX processors, and thus does not support SaGv. Drop the `SaGv` setting from the devicetrees, as it has no effect.
Change-Id: I5be518cce08206ad149efd1665e44a7111b24202 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205 Reviewed-by: Felix Singer felixsinger@posteo.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 52d8f1c..e49ccd7 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -2,7 +2,6 @@
chip soc/intel/cannonlake # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "0"
register "PchHdaDspEnable" = "0" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 37a33e7..f22e42c 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -2,7 +2,6 @@
chip soc/intel/cannonlake # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "0"
register "PchHdaDspEnable" = "0"