David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44903 )
Change subject: mb/google/puff: Update DPTF parameters and TDP PL1/PL2 values ......................................................................
mb/google/puff: Update DPTF parameters and TDP PL1/PL2 values
Update DPTF parameters and TDP PL1/PL2 override to 15W/51W for kaisa and duffy
BUG=b:166696500 TEST=build and verify by thermal team
Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209 Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb 4 files changed, 194 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44903/1
diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl index 6694063..f33dd60 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl @@ -1,3 +1,94 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <puff/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 94 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 68 +#define DPTF_TSR0_CRITICAL 78 +#define DPTF_TSR0_ACTIVE_AC0 65 +#define DPTF_TSR0_ACTIVE_AC1 61 +#define DPTF_TSR0_ACTIVE_AC2 57 +#define DPTF_TSR0_ACTIVE_AC3 53 +#define DPTF_TSR0_ACTIVE_AC4 49 +#define DPTF_TSR0_ACTIVE_AC5 45 +#define DPTF_TSR0_ACTIVE_AC6 41 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + _SB.DPTF.TFN1, _SB.PCI0.TCPU, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 90, 80, 70, 60, 50, 40, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index a4fa09d..5ee3c59 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -1,6 +1,11 @@ chip soc/intel/cannonlake register "tcc_offset" = "5" # TCC of 95C
+ register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1"
diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl index 6694063..f33dd60 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl @@ -1,3 +1,94 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <puff/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 94 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 68 +#define DPTF_TSR0_CRITICAL 78 +#define DPTF_TSR0_ACTIVE_AC0 65 +#define DPTF_TSR0_ACTIVE_AC1 61 +#define DPTF_TSR0_ACTIVE_AC2 57 +#define DPTF_TSR0_ACTIVE_AC3 53 +#define DPTF_TSR0_ACTIVE_AC4 49 +#define DPTF_TSR0_ACTIVE_AC5 45 +#define DPTF_TSR0_ACTIVE_AC6 41 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + _SB.DPTF.TFN1, _SB.PCI0.TCPU, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 90, 80, 70, 60, 50, 40, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index c6aef05..94edb0a 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -1,6 +1,11 @@ chip soc/intel/cannonlake register "tcc_offset" = "5" # TCC of 95C
+ register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1"