HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6813
-gerrit
commit 5f9a90161821e394b3efda5f9d83d8b9aa94cf1a Author: Elyes ehaouas@noos.fr Date: Sun Aug 31 11:13:47 2014 +0200
i945 : Add some comments
FIXME for 945G/945GZ/945GC
Change-Id: Icbf691f33222445e7fcd670e0c6e6c4a9dcaf0aa Signed-off-by: Elyes ehaouas@noos.fr --- src/northbridge/intel/i945/Kconfig | 3 +++ src/northbridge/intel/i945/acpi.c | 2 +- src/northbridge/intel/i945/early_init.c | 18 ++++++++++++++++++ src/northbridge/intel/i945/gma.c | 4 ++-- src/northbridge/intel/i945/northbridge.c | 2 +- src/northbridge/intel/i945/raminit.c | 6 ++++++ 6 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..2ed08bb 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -42,6 +42,9 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config VGA_BIOS_ID string default "8086,27a2" +## FIXME +## default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM +## default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
config CHANNEL_XOR_RANDOMIZATION bool diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index e05bd58..9a7efb7 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -36,7 +36,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses;
- dev = dev_find_device(0x8086, 0x27a0, 0); + dev = dev_find_device(0x8086, 0x27a0, 0); // FIXME for 945G/945GZ/945GC, it should be: dev = dev_find_device(0x8086, 0x2770, 0) if (!dev) return current;
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..b35943e 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,10 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; +// chip i945G +// case 2: +// printk(BIOS_DEBUG, "up to DDR2-667"); +// break; case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,6 +198,11 @@ static void i945_setup_bars(void)
/* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); + +/* FIXME the line below will never happen! +* device (0, 0x0f, 0) do not exist for i945GM/GC/G/P.... +* you can find the CAPID0 register on device (0, 0x00, 0). See mobile-945-express-chipset-datasheet.pdf page 109 +*/ if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; @@ -226,6 +235,9 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ +// FIXME: for i945GC & FSB800MHz, the of (MCHBAR32(CLKCFG) & 7 is equal to 2 and EPBAR32(0x2c)=0x00000014 +// if ((MCHBAR32(CLKCFG) & 7) == 2) +// reg32 = 0x00000014; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +254,12 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; }
+// For i945G/GZ/GC/P/PL & FSB800MHz +// if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ +// EPBAR32(EPVC1IST + 0) = 0x00f000f0; +// EPBAR32(EPVC1IST + 4) = 0x00f000f0; +// } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9b0dbd2..99ea469 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -524,11 +524,11 @@ static struct device_operations gma_func1_ops = { static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a2, + .device = 0x27a2, // FIXME: = 0x2772 for chip 945G/945GZ/945GC };
static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .device = 0x27a6, // FIXME: =0x2776 for chip 945G/945GZ/945GC }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 68d6d91..456d767 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -270,7 +270,7 @@ static struct device_operations mc_ops = { static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a0, + .device = 0x27a0, //FIXME : For chip 945G/945GZ/945GC it is 0x2770 };
static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab..46a5cdc 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -113,6 +113,9 @@ static int memclk(void) offset++; #endif switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { +// FIXME: +// chip i945G/GZ/GC/P/PL & RAM at 667 we have MCHBAR32(0x0c00)= 0x20000032 +// chip i945G/GZ/GC/P/PL & RAM at 533 we have MCHBAR32(0x0c00)= 0x00000022 case 1: return 400; case 2: return 533; case 3: return 667; @@ -2264,6 +2267,9 @@ static void sdram_program_clock_crossing(void)
0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ +//FIXME: value found for 82945G/GZ/GC/P/PL & DDR667 FSB800 : +// 0x04020130, 0x00000008, /* DDR667 FSB800 */ +// and not this one below 0x04020180, 0x00000008, /* DDR667 FSB800 */
0x00020904, 0x00000000, /* DDR400 FSB1066 */