Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35595 )
Change subject: soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35595/2/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/35595/2/src/soc/intel/cannonlake/fs... PS2, Line 207: && params->PchLanEnable
Just checking this should have been sufficient to not set SlpS0WithGbeSupport, right? Do you still n […]
Aah I see in a follow up CL, you are actually using the Vm settings. I think I had this question before but never got a good answer.
How is Voltage margining tied to GbE? Is it that if you have GbE enabled, you need to ignore its state in S0ix and hence disable any kind of voltage margining? Otherwise, you might enable some voltage margining?