[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Assign IOAPIC IDs using FSP

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45115 )

Change subject: soc/amd/picasso: Assign IOAPIC IDs using FSP
......................................................................

soc/amd/picasso: Assign IOAPIC IDs using FSP

Add a Kconfig symbol to use for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync.  The assignment assumes that the
FCH IOAPIC is set to CONFIG_MAX_CPUS and the GNB one is the next
higher.

BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork

Signed-off-by: Marshall Dawson 
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/acpi.c
M src/soc/amd/picasso/fsp_params.c
3 files changed, 16 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45115/1

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index ec5ff76..4a3082b 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -243,6 +243,14 @@
    hex
    default 0xfef00000

+config PICASSO_IOAPIC_IDS
+	hex
+	default MAX_CPUS
+	help
+	  The Picasso APU has two IOAPICs, one in the FCH and one in the
+	  northbridge.  Set this value for the intended ID to assign to the
+	  FCH IOAPIC.  The northbridge's one will be the next higher ID.
+
 config SERIRQ_CONTINUOUS_MODE
    bool
    default n
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 1b9c0ca..0f1a4c2 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -51,7 +51,7 @@

/* Write Kern IOAPIC, only one */
    current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
-			CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+			CONFIG_PICASSO_IOAPIC_IDS, IO_APIC_ADDR, 0);

/* 0: mean bus 0--->ISA */
    /* 0: PIC 0 */
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 1dbb8e5..aeccfca 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -122,6 +122,12 @@
    }
 }

+static void fsp_assign_ioapic_ids(FSP_S_CONFIG *scfg)
+{
+	scfg->fch_ioapic_id = CONFIG_PICASSO_IOAPIC_IDS;
+	scfg->gnb_ioapic_id = CONFIG_PICASSO_IOAPIC_IDS + 1;
+}
+
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
    const struct soc_amd_picasso_config *cfg;
@@ -130,5 +136,6 @@
    cfg = config_of_soc();
    fsps_update_emmc_config(scfg, cfg);
    fsp_fill_pcie_ddi_descriptors(scfg);
+	fsp_assign_ioapic_ids(scfg);
    fsp_usb_oem_customization(scfg, cfg);
 }