[coreboot-gerrit] Change in coreboot[master]: include/cpu/x86/msr: fix MCG_CTL_P definition

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56179 )

Change subject: include/cpu/x86/msr: fix MCG_CTL_P definition
......................................................................

include/cpu/x86/msr: fix MCG_CTL_P definition

MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of
that MSR contain the number of MCA banks being present on the CPU.

Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43
Signed-off-by: Felix Held 
---
M src/include/cpu/x86/msr.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/56179/1

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index bc367d7..f4a28e7 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -36,7 +36,7 @@
 #define SMBASE_RO_MSR			0x98
 #define  IA32_SMM_MONITOR_VALID		(1 << 0)
 #define IA32_MCG_CAP			0x179
-#define  MCG_CTL_P			(1 << 3)
+#define  MCG_CTL_P			(1 << 8)
 #define  MCA_BANKS_MASK			0xff
 #define IA32_PERF_STATUS		0x198
 #define IA32_PERF_CTL			0x199