[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/skylake: Unify serial IRQ options

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31596 )

Change subject: soc/intel/skylake: Unify serial IRQ options
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31596/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31596/2//COMMIT_MSG@20 
PS2, Line 20: A lot of Google boards have serial IRQ enabled, while the pin
            : seems to be unconnected?
> Are you referring to the boards using eSPI?

It's not like you're having your schematics online, do you? ;)
I've been grep'ing for GPP_A6 and got some NC results. poppy,
fizz, eve, on the younger side so probably ESPI, yes. All with
`register "SerialIrqConfigSirqEnable" = "1"`.