Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38640 )
Change subject: cpu: Allow to configure microcode at pre-defined address ......................................................................
cpu: Allow to configure microcode at pre-defined address
FSP-T takes microcode pointer and location parameters, and FSP-T is invoked before CAR is set-up and before memory is trained. So it is not possible to modify supplied microcode pointer in runtime. Because of that we have to hardcode the pointer in bootblock.
Also, current FSP-T on Xeons require microcode (it is not optional). Reasons for that are currently unclear and are being investigated.
However for the present time we need to be able to add microcode at a certain offset so FSP-T can be used.
TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board
Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Signed-off-by: Andrey Petrov anpetrov@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Philipp Deppenwiese zaolin.daisuki@gmail.com --- M src/cpu/Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 4b5d67b..0289be0 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -60,3 +60,7 @@ cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode cpu_microcode_blob.bin-align := 16 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +endif