[coreboot-gerrit] Change in ...coreboot[master]: sb/intel/ibexpeak: Use common final SPI OPs setup

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33038

Change subject: sb/intel/ibexpeak: Use common final SPI OPs setup
......................................................................

sb/intel/ibexpeak: Use common final SPI OPs setup

This also removes the relevant RCBA replays the mainboard dir.

Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6
Signed-off-by: Arthur Heymans 
---
M src/mainboard/lenovo/x201/mainboard.c
M src/mainboard/packardbell/ms2290/mainboard.c
M src/southbridge/intel/ibexpeak/lpc.c
3 files changed, 3 insertions(+), 54 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/33038/1

diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index b8129ad..d39a5bd 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -43,34 +43,6 @@
    return ARRAY_SIZE(cst_entries);
 }

-static void mainboard_init(struct device *dev)
-{
-	printk(BIOS_SPEW, "starting SPI configuration\n");
-
-	/* Configure SPI.  */
-	RCBA32(0x3800) = 0x07ff0500;
-	RCBA32(0x3804) = 0x3f046008;
-	RCBA32(0x3808) = 0x0058efc0;
-	RCBA32(0x384c) = 0x92000000;
-	RCBA32(0x3850) = 0x00000a0b;
-	RCBA32(0x3858) = 0x07ff0500;
-	RCBA32(0x385c) = 0x04ff0003;
-	RCBA32(0x3860) = 0x00020001;
-	RCBA32(0x3864) = 0x00000fff;
-	RCBA32(0x3874) = 0;
-	RCBA32(0x3890) = 0xf8400000;
-	RCBA32(0x3894) = 0x143b5006;
-	RCBA32(0x3898) = 0x05200302;
-	RCBA32(0x389c) = 0x0601209f;
-	RCBA32(0x38b0) = 0x00000004;
-	RCBA32(0x38b4) = 0x03040002;
-	RCBA32(0x38c8) = 0x00002005;
-	RCBA32(0x38c4) = 0x00802005;
-	RCBA32(0x3804) = 0x3f04e008;
-
-	printk(BIOS_SPEW, "SPI configured\n");
-}
-
 static void fill_ssdt(struct device *device)
 {
    drivers_lenovo_serial_ports_ssdt_generate("\_SB.PCI0.LPCB", 0);
@@ -80,7 +52,6 @@
 {
    u16 pmbase;

-	dev->ops->init = mainboard_init;
    dev->ops->acpi_fill_ssdt_generator = fill_ssdt;

pmbase = pci_read_config32(pcidev_on_root(0x1f, 0),
diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c
index 09310ae..6bb546f 100644
--- a/src/mainboard/packardbell/ms2290/mainboard.c
+++ b/src/mainboard/packardbell/ms2290/mainboard.c
@@ -50,31 +50,6 @@
 {
    u16 pmbase;

-	printk(BIOS_SPEW, "starting SPI configuration\n");
-
-	/* Configure SPI.  */
-	RCBA32(0x3800) = 0x07ff0500;
-	RCBA32(0x3804) = 0x3f046008;
-	RCBA32(0x3808) = 0x0058efc0;
-	RCBA32(0x384c) = 0x92000000;
-	RCBA32(0x3850) = 0x00000a0b;
-	RCBA32(0x3858) = 0x07ff0500;
-	RCBA32(0x385c) = 0x04ff0003;
-	RCBA32(0x3860) = 0x00020001;
-	RCBA32(0x3864) = 0x00000fff;
-	RCBA32(0x3874) = 0;
-	RCBA32(0x3890) = 0xf8400000;
-	RCBA32(0x3894) = 0x143b5006;
-	RCBA32(0x3898) = 0x05200302;
-	RCBA32(0x389c) = 0x0601209f;
-	RCBA32(0x38b0) = 0x00000004;
-	RCBA32(0x38b4) = 0x03040002;
-	RCBA32(0x38c8) = 0x00002005;
-	RCBA32(0x38c4) = 0x00802005;
-	RCBA32(0x3804) = 0x3f04e008;
-
-	printk(BIOS_SPEW, "SPI configured\n");
-
    int i;
    const u8 dmp[256] = {
    	0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11,
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index e7162b1..fa1ca92 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -38,6 +38,7 @@
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <southbridge/intel/common/spi.h>

#define NMI_OFF	0

@@ -785,6 +786,8 @@

static void lpc_final(struct device *dev)
 {
+	spi_finalize_ops();
+
    /* Call SMM finalize() handlers before resume */
    if (CONFIG(HAVE_SMI_HANDLER)) {
    	if (CONFIG(INTEL_CHIPSET_LOCKDOWN) ||