Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7264
-gerrit
commit 35cc6c9dbb35a469ffe4cab955d79e9d7a7a3f49 Author: Furquan Shaikh furquan@google.com Date: Thu Apr 10 20:53:32 2014 -0700
ipq806x: Add an include/ folder to ipq806x
Add an include/ folder to hold all the *.h files for ipq806x soc
BUG=None BRANCH=None TEST=Compiled successfully
Original-Change-Id: If07624f126c8d92e479b8f0d9fbc20ab3358a5e3 Original-Reviewed-on: https://chromium-review.googlesource.com/194218 Original-Tested-by: Furquan Shaikh furquan@chromium.org Original-Reviewed-by: Vadim Bendebury vbendeb@chromium.org Original-Commit-Queue: Furquan Shaikh furquan@chromium.org (cherry picked from commit c3c573b6a2d7af504e82b2a02a9869d1d057ce36) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: I42165fca72b48f0d4f15b192d3bfb1574bc73d7c --- src/soc/qualcomm/ipq806x/Makefile.inc | 2 + src/soc/qualcomm/ipq806x/cdp.h | 127 -------------- src/soc/qualcomm/ipq806x/clock.h | 185 -------------------- src/soc/qualcomm/ipq806x/gpio.h | 63 ------- src/soc/qualcomm/ipq806x/gsbi.h | 37 ---- src/soc/qualcomm/ipq806x/include/cdp.h | 127 ++++++++++++++ src/soc/qualcomm/ipq806x/include/clock.h | 185 ++++++++++++++++++++ src/soc/qualcomm/ipq806x/include/gpio.h | 63 +++++++ src/soc/qualcomm/ipq806x/include/gsbi.h | 37 ++++ src/soc/qualcomm/ipq806x/include/iomap.h | 90 ++++++++++ src/soc/qualcomm/ipq806x/include/timer.h | 40 +++++ src/soc/qualcomm/ipq806x/include/uart.h | 281 +++++++++++++++++++++++++++++++ src/soc/qualcomm/ipq806x/iomap.h | 90 ---------- src/soc/qualcomm/ipq806x/timer.h | 40 ----- src/soc/qualcomm/ipq806x/uart.h | 281 ------------------------------- 15 files changed, 825 insertions(+), 823 deletions(-)
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 0ea2996..35ff932 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -26,3 +26,5 @@ $(objcbfs)/bootblock.bin: ./$(call strip_quotes,$(CONFIG_SBL_BLOB)) \ @mv $@.tmp $@
endif + +INCLUDES += -Isrc/soc/qualcomm/ipq806x/include diff --git a/src/soc/qualcomm/ipq806x/cdp.h b/src/soc/qualcomm/ipq806x/cdp.h deleted file mode 100644 index 4ae476a..0000000 --- a/src/soc/qualcomm/ipq806x/cdp.h +++ /dev/null @@ -1,127 +0,0 @@ -/* * Copyright (c) 2012 The Linux Foundation. All rights reserved.* */ - - -#ifndef _IPQ806X_CDP_H_ -#define _IPQ806X_CDP_H_ - -#include <phy.h> - -unsigned int smem_get_board_machtype(void); - -typedef struct { - unsigned int gpio; - unsigned int func; - unsigned int dir; - unsigned int pull; - unsigned int drvstr; - unsigned int enable; -} gpio_func_data_t; - -typedef struct { - unsigned int m_value; - unsigned int n_value; - unsigned int d_value; -} uart_clk_mnd_t; - -/* SPI Mode */ - -typedef enum { - NOR_SPI_MODE_0, - NOR_SPI_MODE_1, - NOR_SPI_MODE_2, - NOR_SPI_MODE_3, -} spi_mode; - -/* SPI GSBI Bus number */ - -typedef enum { - GSBI_BUS_5 = 0, - GSBI_BUS_6, - GSBI_BUS_7, -} spi_gsbi_bus_num; - -/* SPI Chip selects */ - -typedef enum { - SPI_CS_0 , - SPI_CS_1, - SPI_CS_2, - SPI_CS_3, -} spi_cs; - -/* Flash Types */ - -typedef enum { - ONLY_NAND, - ONLY_NOR, - NAND_NOR, - NOR_MMC, -} flash_desc; - -#define NO_OF_DBG_UART_GPIOS 2 - -#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 -#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 - -/* SPI parameters */ - -typedef struct { - spi_mode mode; - spi_gsbi_bus_num bus_number; - spi_cs chip_select; - int vendor; -} spinorflash_params_t; - -typedef struct { - uint count; - u8 addr[7]; -} ipq_gmac_phy_addr_t; - -typedef struct { - uint base; - int unit; - uint is_macsec; - uint mac_pwr0; - uint mac_pwr1; - uint mac_conn_to_phy; - phy_interface_t phy; - ipq_gmac_phy_addr_t phy_addr; -} ipq_gmac_board_cfg_t; - -#define IPQ_GMAC_NMACS 4 - -/* Board specific parameters */ -typedef struct { - unsigned int machid; - unsigned int ddr_size; - unsigned int uart_gsbi; - unsigned int uart_gsbi_base; - unsigned int uart_dm_base; - unsigned int clk_dummy; - uart_clk_mnd_t mnd_value; - unsigned int gmac_gpio_count; - gpio_func_data_t *gmac_gpio; - ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; - flash_desc flashdesc; - spinorflash_params_t flash_param; - gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; -} __attribute__ ((__packed__)) board_ipq806x_params_t; - -extern board_ipq806x_params_t *gboard_param; - -static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) -{ - /* - * 'cfg' is valid if and only if - * unit number is non-negative and less than IPQ_GMAC_NMACS. - * 'cfg' pointer lies within the array range of - * board_ipq806x_params_t->gmac_cfg[] - */ - return ((cfg >= &gboard_param->gmac_cfg[0]) && - (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && - (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); -} - -unsigned int get_board_index(unsigned int machid); -void ipq_configure_gpio(gpio_func_data_t *gpio, uint count); -#endif diff --git a/src/soc/qualcomm/ipq806x/clock.h b/src/soc/qualcomm/ipq806x/clock.h deleted file mode 100644 index 263b81b..0000000 --- a/src/soc/qualcomm/ipq806x/clock.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK Boot - * - * Copyright (c) 2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PLATFORM_IPQ860X_CLOCK_H_ -#define __PLATFORM_IPQ860X_CLOCK_H_ - -#include <asm/io.h> -/* UART clock @ 7.3728 MHz */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC - -/* UART specific definitions */ - -#define BIT(s) (1<<s) -#define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) -#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) -#define Uart_mnd_en_mask BIT(8) * !!(625) -#define Uart_en_mask BIT(11) -#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n))) -#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0) -#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) -#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) -#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) -#define BB_PLL_ENA_SC0_REG REG(0x34C0) -#define BB_PLL8_STATUS_REG REG(0x3158) -#define REG(off) (MSM_CLK_CTL_BASE + (off)) -#define PLL8_STATUS_BIT 16 - -#define PLL_LOCK_DET_STATUS_REG REG(0x03420) -#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C) -#define CFPB_CLK_NS_REG REG(0x0264C) -#define CFPB0_HCLK_CTL_REG REG(0x02650) -#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0) -#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0) -#define EBI2_CLK_CTL_REG REG(0x03B00) - -#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8) - -#define CLK_BRANCH_ENA_MASK 0x00000010 -#define CLK_BRANCH_ENA_ENABLE 0x00000010 -#define CLK_BRANCH_ENA_DISABLE 0x00000000 -#define CLK_BRANCH_ENA(i) ((i) << 4) - -/* Register: CFPB_CLK_NS */ -#define CLK_DIV_MASK 0x00000003 -#define CLK_DIV_DIV_1 0x00000000 -#define CLK_DIV_DIV_2 0x00000001 -#define CLK_DIV_DIV_3 0x00000002 -#define CLK_DIV_DIV_4 0x00000003 -#define CLK_DIV(i) ((i) << 0) - -#define MN_MODE_DUAL_EDGE 0x2 -#define BIT_POS_31 31 -#define BIT_POS_16 16 -#define BIT_POS_6 6 -#define BIT_POS_0 0 -#define BIT_POS_15 15 - -#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l) -#define BVAL(m, l, val) (((val) << l) & BM(m, l)) - -/* MD Registers */ -#define MD4(m_lsb, m, n_lsb, n) \ - (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n))) - -#define MD8(m_lsb, m, n_lsb, n) \ - (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n))) - -/* NS Registers */ -#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(n_msb, n_lsb, ~(n-m)) \ - | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \ - | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) - -#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \ - | BVAL(s_msb, s_lsb, s)) - -#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) - -#define NS_DIV(d_msb , d_lsb, d) \ - BVAL(d_msb, d_lsb, (d-1)) - -#define NS_SRC_SEL(s_msb, s_lsb, s) \ - BVAL(s_msb, s_lsb, s) - -#define GMAC_AHB_RESET 0x903E24 - -#define SRC_SEL_PLL0 (0x2 << 0) -#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) -#define MNCNTR_ENABLE (0x1 << 8) -#define MNCNTR_RST_ACTIVE (0x1 << 7) -#define N_VAL 15 - -#define GMAC_CORE_RESET(n) \ - ((void *)(0x903CBC + ((n) * 0x20))) - -#define GMACSEC_CORE_RESET(n) \ - ((void *)(0x903E28 + ((n - 1) * 4))) - -#define GMAC_COREn_CLCK_SRC_CTL(N) \ - (0x00900000 + (0x3CA0 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC0_MD(N) \ - (0x00900000 + (0x3CA4 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC1_MD(N) \ - (0x00900000 + (0x3CA8 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC0_NS(N) \ - (0x00900000 + (0x3CAC + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC1_NS(N) \ - (0x00900000 + (0x3CB0 + (32*(N-1)))) - -#define DISABLE_DUAL_MN8_SEL (0) -#define DISABLE_CLK_LOW_PWR (0 << 2) -#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1) - -/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */ -#define GMAC_CORE_CLCK_M 0x32 -#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */ -#define GMAC_CORE_CLCK_M_SHIFT 16 -#define GMAC_CORE_CLCK_D_SHIFT 0 -#define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT) -#define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT) - -/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */ -#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */ -#define GMAC_CORE_CLCK_N_SHIFT 16 -#define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT) -#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */ -#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */ -#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */ -#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5 -#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */ -#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */ -#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3 -#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */ -#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */ -#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0 -#define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */ -#define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) -#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) - - -/* Uart specific clock settings */ - -void uart_pll_vote_clk_enable(unsigned int); -void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, - unsigned int d, unsigned int clk_dummy); -void nand_clock_config(void); - -#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/gpio.h b/src/soc/qualcomm/ipq806x/gpio.h deleted file mode 100644 index e2b281e..0000000 --- a/src/soc/qualcomm/ipq806x/gpio.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* - Source : APQ8064 LK Boot - - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PLATFORM_AKRONITE_GPIO_H_ -#define __PLATFORM_AKRONITE_GPIO_H_ - -/* GPIO TLMM: Direction */ -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 - -/* GPIO TLMM: Pullup/Pulldown */ -#define GPIO_NO_PULL 0 -#define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 - -/* GPIO TLMM: Drive Strength */ -#define GPIO_2MA 0 -#define GPIO_4MA 1 -#define GPIO_6MA 2 -#define GPIO_8MA 3 -#define GPIO_10MA 4 -#define GPIO_12MA 5 -#define GPIO_14MA 6 -#define GPIO_16MA 7 - -/* GPIO TLMM: Status */ -#define GPIO_ENABLE 0 -#define GPIO_DISABLE 1 - -void gpio_tlmm_config(unsigned int gpio, unsigned int func, - unsigned int dir, unsigned int pull, - unsigned int drvstr, unsigned int enable); -#endif diff --git a/src/soc/qualcomm/ipq806x/gsbi.h b/src/soc/qualcomm/ipq806x/gsbi.h deleted file mode 100644 index d2ba2b3..0000000 --- a/src/soc/qualcomm/ipq806x/gsbi.h +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (c) 2004-2011 Atheros Communications Inc. -* Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - - -#ifndef __GSBI_H_ -#define __GSBI_H_ - -#include <asm/io.h> - -/* GSBI Registers */ -#define GSBI_CTRL_REG(base) ((base) + 0x0) - -#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4 -#define GSBI_PROTOCOL_CODE_I2C 0x2 -#define GSBI_PROTOCOL_CODE_SPI 0x3 -#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4 -#define GSBI_PROTOCOL_CODE_I2C_UART 0x6 - -#define GSBI_HCLK_CTL_S 4 -#define GSBI_HCLK_CTL_CLK_ENA 0x1 - -#endif - diff --git a/src/soc/qualcomm/ipq806x/include/cdp.h b/src/soc/qualcomm/ipq806x/include/cdp.h new file mode 100644 index 0000000..4ae476a --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/cdp.h @@ -0,0 +1,127 @@ +/* * Copyright (c) 2012 The Linux Foundation. All rights reserved.* */ + + +#ifndef _IPQ806X_CDP_H_ +#define _IPQ806X_CDP_H_ + +#include <phy.h> + +unsigned int smem_get_board_machtype(void); + +typedef struct { + unsigned int gpio; + unsigned int func; + unsigned int dir; + unsigned int pull; + unsigned int drvstr; + unsigned int enable; +} gpio_func_data_t; + +typedef struct { + unsigned int m_value; + unsigned int n_value; + unsigned int d_value; +} uart_clk_mnd_t; + +/* SPI Mode */ + +typedef enum { + NOR_SPI_MODE_0, + NOR_SPI_MODE_1, + NOR_SPI_MODE_2, + NOR_SPI_MODE_3, +} spi_mode; + +/* SPI GSBI Bus number */ + +typedef enum { + GSBI_BUS_5 = 0, + GSBI_BUS_6, + GSBI_BUS_7, +} spi_gsbi_bus_num; + +/* SPI Chip selects */ + +typedef enum { + SPI_CS_0 , + SPI_CS_1, + SPI_CS_2, + SPI_CS_3, +} spi_cs; + +/* Flash Types */ + +typedef enum { + ONLY_NAND, + ONLY_NOR, + NAND_NOR, + NOR_MMC, +} flash_desc; + +#define NO_OF_DBG_UART_GPIOS 2 + +#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 +#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 + +/* SPI parameters */ + +typedef struct { + spi_mode mode; + spi_gsbi_bus_num bus_number; + spi_cs chip_select; + int vendor; +} spinorflash_params_t; + +typedef struct { + uint count; + u8 addr[7]; +} ipq_gmac_phy_addr_t; + +typedef struct { + uint base; + int unit; + uint is_macsec; + uint mac_pwr0; + uint mac_pwr1; + uint mac_conn_to_phy; + phy_interface_t phy; + ipq_gmac_phy_addr_t phy_addr; +} ipq_gmac_board_cfg_t; + +#define IPQ_GMAC_NMACS 4 + +/* Board specific parameters */ +typedef struct { + unsigned int machid; + unsigned int ddr_size; + unsigned int uart_gsbi; + unsigned int uart_gsbi_base; + unsigned int uart_dm_base; + unsigned int clk_dummy; + uart_clk_mnd_t mnd_value; + unsigned int gmac_gpio_count; + gpio_func_data_t *gmac_gpio; + ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; + flash_desc flashdesc; + spinorflash_params_t flash_param; + gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; +} __attribute__ ((__packed__)) board_ipq806x_params_t; + +extern board_ipq806x_params_t *gboard_param; + +static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) +{ + /* + * 'cfg' is valid if and only if + * unit number is non-negative and less than IPQ_GMAC_NMACS. + * 'cfg' pointer lies within the array range of + * board_ipq806x_params_t->gmac_cfg[] + */ + return ((cfg >= &gboard_param->gmac_cfg[0]) && + (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && + (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); +} + +unsigned int get_board_index(unsigned int machid); +void ipq_configure_gpio(gpio_func_data_t *gpio, uint count); +#endif diff --git a/src/soc/qualcomm/ipq806x/include/clock.h b/src/soc/qualcomm/ipq806x/include/clock.h new file mode 100644 index 0000000..263b81b --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/clock.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK Boot + * + * Copyright (c) 2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_IPQ860X_CLOCK_H_ +#define __PLATFORM_IPQ860X_CLOCK_H_ + +#include <asm/io.h> +/* UART clock @ 7.3728 MHz */ +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC + +/* UART specific definitions */ + +#define BIT(s) (1<<s) +#define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) +#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) +#define Uart_mnd_en_mask BIT(8) * !!(625) +#define Uart_en_mask BIT(11) +#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n))) +#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0) +#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) +#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) +#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) +#define BB_PLL_ENA_SC0_REG REG(0x34C0) +#define BB_PLL8_STATUS_REG REG(0x3158) +#define REG(off) (MSM_CLK_CTL_BASE + (off)) +#define PLL8_STATUS_BIT 16 + +#define PLL_LOCK_DET_STATUS_REG REG(0x03420) +#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C) +#define CFPB_CLK_NS_REG REG(0x0264C) +#define CFPB0_HCLK_CTL_REG REG(0x02650) +#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0) +#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0) +#define EBI2_CLK_CTL_REG REG(0x03B00) + +#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8) + +#define CLK_BRANCH_ENA_MASK 0x00000010 +#define CLK_BRANCH_ENA_ENABLE 0x00000010 +#define CLK_BRANCH_ENA_DISABLE 0x00000000 +#define CLK_BRANCH_ENA(i) ((i) << 4) + +/* Register: CFPB_CLK_NS */ +#define CLK_DIV_MASK 0x00000003 +#define CLK_DIV_DIV_1 0x00000000 +#define CLK_DIV_DIV_2 0x00000001 +#define CLK_DIV_DIV_3 0x00000002 +#define CLK_DIV_DIV_4 0x00000003 +#define CLK_DIV(i) ((i) << 0) + +#define MN_MODE_DUAL_EDGE 0x2 +#define BIT_POS_31 31 +#define BIT_POS_16 16 +#define BIT_POS_6 6 +#define BIT_POS_0 0 +#define BIT_POS_15 15 + +#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l) +#define BVAL(m, l, val) (((val) << l) & BM(m, l)) + +/* MD Registers */ +#define MD4(m_lsb, m, n_lsb, n) \ + (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n))) + +#define MD8(m_lsb, m, n_lsb, n) \ + (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n))) + +/* NS Registers */ +#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(n_msb, n_lsb, ~(n-m)) \ + | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \ + | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) + +#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \ + | BVAL(s_msb, s_lsb, s)) + +#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) + +#define NS_DIV(d_msb , d_lsb, d) \ + BVAL(d_msb, d_lsb, (d-1)) + +#define NS_SRC_SEL(s_msb, s_lsb, s) \ + BVAL(s_msb, s_lsb, s) + +#define GMAC_AHB_RESET 0x903E24 + +#define SRC_SEL_PLL0 (0x2 << 0) +#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) +#define MNCNTR_ENABLE (0x1 << 8) +#define MNCNTR_RST_ACTIVE (0x1 << 7) +#define N_VAL 15 + +#define GMAC_CORE_RESET(n) \ + ((void *)(0x903CBC + ((n) * 0x20))) + +#define GMACSEC_CORE_RESET(n) \ + ((void *)(0x903E28 + ((n - 1) * 4))) + +#define GMAC_COREn_CLCK_SRC_CTL(N) \ + (0x00900000 + (0x3CA0 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC0_MD(N) \ + (0x00900000 + (0x3CA4 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC1_MD(N) \ + (0x00900000 + (0x3CA8 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC0_NS(N) \ + (0x00900000 + (0x3CAC + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC1_NS(N) \ + (0x00900000 + (0x3CB0 + (32*(N-1)))) + +#define DISABLE_DUAL_MN8_SEL (0) +#define DISABLE_CLK_LOW_PWR (0 << 2) +#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1) + +/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */ +#define GMAC_CORE_CLCK_M 0x32 +#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */ +#define GMAC_CORE_CLCK_M_SHIFT 16 +#define GMAC_CORE_CLCK_D_SHIFT 0 +#define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT) +#define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT) + +/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */ +#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */ +#define GMAC_CORE_CLCK_N_SHIFT 16 +#define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT) +#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */ +#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */ +#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */ +#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5 +#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */ +#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */ +#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3 +#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */ +#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */ +#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0 +#define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */ +#define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) +#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) + + +/* Uart specific clock settings */ + +void uart_pll_vote_clk_enable(unsigned int); +void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, + unsigned int d, unsigned int clk_dummy); +void nand_clock_config(void); + +#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/gpio.h b/src/soc/qualcomm/ipq806x/include/gpio.h new file mode 100644 index 0000000..e2b281e --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/gpio.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + Source : APQ8064 LK Boot + + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_AKRONITE_GPIO_H_ +#define __PLATFORM_AKRONITE_GPIO_H_ + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_ENABLE 0 +#define GPIO_DISABLE 1 + +void gpio_tlmm_config(unsigned int gpio, unsigned int func, + unsigned int dir, unsigned int pull, + unsigned int drvstr, unsigned int enable); +#endif diff --git a/src/soc/qualcomm/ipq806x/include/gsbi.h b/src/soc/qualcomm/ipq806x/include/gsbi.h new file mode 100644 index 0000000..d2ba2b3 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/gsbi.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2004-2011 Atheros Communications Inc. +* Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + + +#ifndef __GSBI_H_ +#define __GSBI_H_ + +#include <asm/io.h> + +/* GSBI Registers */ +#define GSBI_CTRL_REG(base) ((base) + 0x0) + +#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4 +#define GSBI_PROTOCOL_CODE_I2C 0x2 +#define GSBI_PROTOCOL_CODE_SPI 0x3 +#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4 +#define GSBI_PROTOCOL_CODE_I2C_UART 0x6 + +#define GSBI_HCLK_CTL_S 4 +#define GSBI_HCLK_CTL_CLK_ENA 0x1 + +#endif + diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h new file mode 100644 index 0000000..514c6a7 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _PLATFORM_MSM8960_IOMAP_H_ +#define _PLATFORM_MSM8960_IOMAP_H_ + +#include <configs/ipq806x_cdp.h> +#define MSM_CLK_CTL_BASE 0x00900000 + +#define MSM_TMR_BASE 0x0200A000 +#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) + +#define GPT_REG(off) (MSM_GPT_BASE + (off)) +#define DGT_REG(off) (MSM_DGT_BASE + (off)) + +#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) +#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038) +#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C) +#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C) + +#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820) + +#define GPT_MATCH_VAL GPT_REG(0x0000) +#define GPT_COUNT_VAL GPT_REG(0x0004) +#define GPT_ENABLE GPT_REG(0x0008) +#define GPT_CLEAR GPT_REG(0x000C) + +#define GPT1_MATCH_VAL GPT_REG(0x00010) +#define GPT1_COUNT_VAL GPT_REG(0x00014) +#define GPT1_ENABLE GPT_REG(0x00018) +#define GPT1_CLEAR GPT_REG(0x0001C) + +#define DGT_MATCH_VAL DGT_REG(0x0000) +#define DGT_COUNT_VAL DGT_REG(0x0004) +#define DGT_ENABLE DGT_REG(0x0008) +#define DGT_CLEAR DGT_REG(0x000C) +#define DGT_CLK_CTL DGT_REG(0x0010) + +#define TLMM_BASE_ADDR 0x00800000 +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) +#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) + +#define GSBI_1 1 +#define GSBI_2 2 +#define GSBI_4 4 +#define GSBI_2 2 +#define UART1_DM_BASE 0x12450000 +#define UART_GSBI1_BASE 0x12440000 +#define UART2_DM_BASE 0x12490000 +#define UART_GSBI2_BASE 0x12480000 +#define UART4_DM_BASE 0x16340000 +#define UART_GSBI4_BASE 0x16300000 + +#define UART2_DM_BASE 0x12490000 +#define UART_GSBI2_BASE 0x12480000 + +#endif diff --git a/src/soc/qualcomm/ipq806x/include/timer.h b/src/soc/qualcomm/ipq806x/include/timer.h new file mode 100644 index 0000000..4e1ef34 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/timer.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define TIMER_LOAD_VAL 0x21 + +#define GPT_ENABLE_CLR_ON_MATCH_EN 2 +#define GPT_ENABLE_EN 1 +#define DGT_ENABLE_CLR_ON_MATCH_EN 2 +#define DGT_ENABLE_EN 1 + +#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) + + diff --git a/src/soc/qualcomm/ipq806x/include/uart.h b/src/soc/qualcomm/ipq806x/include/uart.h new file mode 100644 index 0000000..6fff046 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/uart.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + * + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#include <asm/io.h> +#include "common.h" +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos))\ + >> (32 - (end_pos - start_pos))) + + +extern void dsb(void); +#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \ + word = 0; \ + int j; \ + for(j=0; j < (int)cnt; j++) { \ + word |= (a[j] & 0xff)<< (j * 8);\ + } \ + } + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ + | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +#endif /* __UART_DM_H__ */ + diff --git a/src/soc/qualcomm/ipq806x/iomap.h b/src/soc/qualcomm/ipq806x/iomap.h deleted file mode 100644 index 514c6a7..0000000 --- a/src/soc/qualcomm/ipq806x/iomap.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * - * Copyright (c) 2008, Google Inc. - * All rights reserved. - * - * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _PLATFORM_MSM8960_IOMAP_H_ -#define _PLATFORM_MSM8960_IOMAP_H_ - -#include <configs/ipq806x_cdp.h> -#define MSM_CLK_CTL_BASE 0x00900000 - -#define MSM_TMR_BASE 0x0200A000 -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) - -#define GPT_REG(off) (MSM_GPT_BASE + (off)) -#define DGT_REG(off) (MSM_DGT_BASE + (off)) - -#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) -#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038) -#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C) -#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C) - -#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820) - -#define GPT_MATCH_VAL GPT_REG(0x0000) -#define GPT_COUNT_VAL GPT_REG(0x0004) -#define GPT_ENABLE GPT_REG(0x0008) -#define GPT_CLEAR GPT_REG(0x000C) - -#define GPT1_MATCH_VAL GPT_REG(0x00010) -#define GPT1_COUNT_VAL GPT_REG(0x00014) -#define GPT1_ENABLE GPT_REG(0x00018) -#define GPT1_CLEAR GPT_REG(0x0001C) - -#define DGT_MATCH_VAL DGT_REG(0x0000) -#define DGT_COUNT_VAL DGT_REG(0x0004) -#define DGT_ENABLE DGT_REG(0x0008) -#define DGT_CLEAR DGT_REG(0x000C) -#define DGT_CLK_CTL DGT_REG(0x0010) - -#define TLMM_BASE_ADDR 0x00800000 -#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) -#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) - -#define GSBI_1 1 -#define GSBI_2 2 -#define GSBI_4 4 -#define GSBI_2 2 -#define UART1_DM_BASE 0x12450000 -#define UART_GSBI1_BASE 0x12440000 -#define UART2_DM_BASE 0x12490000 -#define UART_GSBI2_BASE 0x12480000 -#define UART4_DM_BASE 0x16340000 -#define UART_GSBI4_BASE 0x16300000 - -#define UART2_DM_BASE 0x12490000 -#define UART_GSBI2_BASE 0x12480000 - -#endif diff --git a/src/soc/qualcomm/ipq806x/timer.h b/src/soc/qualcomm/ipq806x/timer.h deleted file mode 100644 index 4e1ef34..0000000 --- a/src/soc/qualcomm/ipq806x/timer.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#define TIMER_LOAD_VAL 0x21 - -#define GPT_ENABLE_CLR_ON_MATCH_EN 2 -#define GPT_ENABLE_EN 1 -#define DGT_ENABLE_CLR_ON_MATCH_EN 2 -#define DGT_ENABLE_EN 1 - -#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) - - diff --git a/src/soc/qualcomm/ipq806x/uart.h b/src/soc/qualcomm/ipq806x/uart.h deleted file mode 100644 index 6fff046..0000000 --- a/src/soc/qualcomm/ipq806x/uart.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* - * - * Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __UART_DM_H__ -#define __UART_DM_H__ - -#include <asm/io.h> -#include "common.h" -#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ - ((value << (32 - end_pos))\ - >> (32 - (end_pos - start_pos))) - - -extern void dsb(void); -#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \ - word = 0; \ - int j; \ - for(j=0; j < (int)cnt; j++) { \ - word |= (a[j] & 0xff)<< (j * 8);\ - } \ - } - -extern void __udelay(unsigned long usec); - - -enum MSM_BOOT_UART_DM_PARITY_MODE { - MSM_BOOT_UART_DM_NO_PARITY, - MSM_BOOT_UART_DM_ODD_PARITY, - MSM_BOOT_UART_DM_EVEN_PARITY, - MSM_BOOT_UART_DM_SPACE_PARITY -}; - -/* UART Stop Bit Length */ -enum MSM_BOOT_UART_DM_STOP_BIT_LEN { - MSM_BOOT_UART_DM_SBL_9_16, - MSM_BOOT_UART_DM_SBL_1, - MSM_BOOT_UART_DM_SBL_1_9_16, - MSM_BOOT_UART_DM_SBL_2 -}; - -/* UART Bits per Char */ -enum MSM_BOOT_UART_DM_BITS_PER_CHAR { - MSM_BOOT_UART_DM_5_BPS, - MSM_BOOT_UART_DM_6_BPS, - MSM_BOOT_UART_DM_7_BPS, - MSM_BOOT_UART_DM_8_BPS -}; - -/* 8-N-1 Configuration */ -#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ - (MSM_BOOT_UART_DM_SBL_1 << 2) | \ - (MSM_BOOT_UART_DM_8_BPS << 4)) - -/* UART_DM Registers */ - -/* UART Operational Mode Register */ -#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) -#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) -#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) -#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) - -/* UART Clock Selection Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) -#else -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) -#endif - -/* UART DM TX FIFO Registers - 4 */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) -#else -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) -#endif - -/* UART Command Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) -#else -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) -#endif -#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) -#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) -#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) -#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) - -/* UART Channel Command */ -#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) -#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) -#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ - | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) -#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) -#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) -#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) -#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) -#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) -#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) -#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) -#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) -#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) -#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) -#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) -#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) -#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) -#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) -#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) -#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) -#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) -#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) - -/*UART General Command */ -#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) - -#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) -#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) -#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) -#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) -#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) - -/* UART Interrupt Mask Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) -#else -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) -#endif - -#define MSM_BOOT_UART_DM_TXLEV (1 << 0) -#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) -#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) -#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) -#define MSM_BOOT_UART_DM_RXLEV (1 << 4) -#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) -#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) -#define MSM_BOOT_UART_DM_TX_READY (1 << 7) -#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) -#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) -#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) -#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) -#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) - -#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ - MSM_BOOT_UART_DM_TXLEV | \ - MSM_BOOT_UART_DM_RXSTALE) - -/* UART Interrupt Programming Register */ -#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ - -/* UART Transmit/Receive FIFO Watermark Register */ -#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) -/* Interrupt is generated when FIFO level is less than or equal to this value */ -#define MSM_BOOT_UART_DM_TFW_VALUE 0 - -#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) -/*Interrupt generated when no of words in RX FIFO is greater than this value */ -#define MSM_BOOT_UART_DM_RFW_VALUE 0 - -/* UART Hunt Character Register */ -#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) - -/* Used for RX transfer initialization */ -#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) - -/* Default DMRX value - any value bigger than FIFO size would be fine */ -#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 - -/* Register to enable IRDA function */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) -#else -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) -#endif - -/* UART Data Mover Enable Register */ -#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) - -/* Number of characters for Transmission */ -#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) - -/* UART RX FIFO Base Address */ -#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) - -/* UART Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) -#else -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) -#endif -#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) -#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) -#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) -#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) -#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) -#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) -#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) -#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) -#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) - -/* UART Receive FIFO Registers - 4 in numbers */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) -#else -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) -#endif - -/* UART Masked Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) -#else -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) -#endif - -/* UART Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) -#else -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) -#endif - -/* Number of characters received since the end of last RX transfer */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) -#else -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) -#endif - -/* UART TX FIFO Status Register */ -#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) -#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* UART RX FIFO Status Register */ -#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) -#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* Macros for Common Errors */ -#define MSM_BOOT_UART_DM_E_SUCCESS 0 -#define MSM_BOOT_UART_DM_E_FAILURE 1 -#define MSM_BOOT_UART_DM_E_TIMEOUT 2 -#define MSM_BOOT_UART_DM_E_INVAL 3 -#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 -#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 - -#endif /* __UART_DM_H__ */ -