[coreboot-gerrit] Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code

[Aamir Bohra (Code Review)]

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49732 )

Change subject: mb/intel/shadowmountain: Add the ramstage code
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Patch Set 3:

(2 comments)

File src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c:

https://review.coreboot.org/c/coreboot/+/49732/comment/07a93f63_25386506 
PS3, Line 33: 	/* D15 : MEM_STRAP_3 */
            : 	PAD_CFG_GPI(GPP_D15, NONE, DEEP),
can be marked NC, only 0, 1, 2 are been used for memory straps.

File src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/49732/comment/5305e4d0_e08ebd1f 
PS3, Line 164: 	/* E10 : PCH_GSPI0_H1_TPM_CS_L */
             : 	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
             : 	/* E11 : PCH_GSPI0_H1_TPM_CLK */
             : 	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
             : 	/* E12 : PCH_GSPIO_H1_TPM_MISO */
             : 	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
             : 	/* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
             : 	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
can be skipped , part of early gpio table.