[coreboot-gerrit] Change in coreboot[master]: device/pciexp: Match Max_Payload_Size between ends of a link

[Kyösti Mälkki (Code Review)]

Hello Aaron Durbin, Aamir Bohra, Marshall Dawson, Дмитрий Понаморев, build bot (Jenkins), Nico Huber,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37769

to look at the new patch set (#2).

Change subject: device/pciexp: Match Max_Payload_Size between ends of a link
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device/pciexp: Match Max_Payload_Size between ends of a link

Ends of a PCIe link may advertise different Max_Payload_Size in
their PCIe Express Capabilities, Device Capabilities block.

For correct operation, both ends of the link need to have their
Device Control Max_Payload_Size programmed to match and not
exceed the other end's Device Capabilities.

Fixes: https://ticket.coreboot.org/issues/218

Change-Id: I8b1de13e9c73abb30e5ccc792918bb4f81e5fe84
Signed-off-by: Kyösti Mälkki 
---
M src/device/pciexp_device.c
1 file changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37769/2