Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/32880 )
Change subject: soc/fsp_broadwell_de: fix flashconsole support for platform ......................................................................
soc/fsp_broadwell_de: fix flashconsole support for platform
CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506.
Revert the changes back to usage of CAR_GLOBAL in the common spi driver so that flashconsole will work again in romsatge for fsp_broadwell_de.
Test: verify flashconsole functional on out-of-tree Broadwell-DE board
Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier matt.devillier@gmail.com Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c 1 file changed, 18 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Arthur Heymans: Looks good to me, approved
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 6569351..268030b 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -16,6 +16,7 @@ */
/* This file is derived from the flashrom project. */ +#include <arch/early_variables.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -109,7 +110,7 @@ uint8_t fpr_max; };
-static struct ich_spi_controller g_cntlr; +static struct ich_spi_controller g_cntlr CAR_GLOBAL;
enum { SPIS_SCIP = 0x0001, @@ -254,7 +255,7 @@
static void ich_set_bbar(uint32_t minaddr) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar;
@@ -272,7 +273,7 @@
void spi_init(void) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; @@ -414,7 +415,7 @@
static int spi_setup_opcode(spi_transaction *trans) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; uint8_t opmenu[MENU_BYTES];
@@ -494,7 +495,7 @@ */ static int ich_status_poll(u16 bitmask, int wait_til_set) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 600000; /* This will result in 6 seconds */ u16 status = 0;
@@ -515,7 +516,7 @@
static int spi_is_multichip(void) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); if (!(cntlr->hsfs & HSFS_FDV)) return 0; return !!((cntlr->flmap0 >> 8) & 3); @@ -524,7 +525,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -674,7 +675,7 @@ /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); @@ -687,7 +688,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, unsigned int len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfs; uint32_t addr;
@@ -727,7 +728,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start, end, erase_size; int ret; uint16_t hsfc; @@ -777,7 +778,7 @@
static void ich_read_data(uint8_t *data, int len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int i; uint32_t temp32 = 0;
@@ -792,7 +793,7 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -838,7 +839,7 @@ */ static void ich_fill_data(const uint8_t *data, int len) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t temp32 = 0; int i;
@@ -862,7 +863,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, const void *buf) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -918,7 +919,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, struct spi_flash *flash) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return spi_flash_generic_probe(spi, flash); @@ -998,7 +999,7 @@ const struct region *region, const enum ctrlr_prot_type type) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start = region_offset(region); u32 end = start + region_sz(region) - 1; u32 reg; @@ -1056,7 +1057,7 @@
void spi_finalize_ops(void) { - struct ich_spi_controller *cntlr = &g_cntlr; + struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u16 spi_opprefix; u16 optype = 0; struct intel_swseq_spi_config spi_config = {