[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update TCSS PM flow

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45014 )

Change subject: soc/intel/tigerlake: Update TCSS PM flow
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45014/3/src/soc/intel/tigerlake/acp... 
File src/soc/intel/tigerlake/acpi/tcss.asl:

https://review.coreboot.org/c/coreboot/+/45014/3/src/soc/intel/tigerlake/acp... 
PS3, Line 622: 2
> Is '2' (or '3' above) just for debugging? Because the _PS0 method only cares if SCMP is 1, so why no […]

It is about keep tracking PM flow: D0(SCMP=0) -> D3 hot(SCMP=0) -> _PS3 (SCMP=1) -> _OFF(SCMP=2) -> _ON (SCMP=3) ->_PS0(SCMP=0). If simply setting SCMP to 0, we have no clue about the PM flow stage. You are right, it is also good for debugging.