Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )
Change subject: arch/x86: Cache the TSEG region at the top of ram ......................................................................
Patch Set 4:
Patch Set 4:
Patch Set 4:
Aaron, please visit CB:34805 patchset #6 comments and how you wish to address the alignment requirement about parameters passed to postcar_frame_setup_top_of_dram_usage(), if it will be extended to call set_var_mtrr().
Ya. I'm not sure we're in agreement on the best option forward there. Thanks for the pointer.
Subrata, can we have cbmem -t for this commit posted as well. My concern is that after all this work, POSTCAR_STAGE=y is still the better performing solution, winning POSTCAR_STAGE=n by some 7 ms.
I'm thinking that might be true as well. Anyway, we can have the discussion on that commit.
There are two topic branches; x86-smm-tseg and x86-romstage together already form a unified function/file layout over TSEG. IMHO those should go in first before discussing an API to set TSEG regions WB cacheable. I believe I also saw some numbers suggesting write-combining for TSEG would give the same performance boost without consuming cachelines at end of romstage. I did not find (or really look for) that data now, but it sort of makes sense as TSEG_STAGE_CACHE is mostly writes to TSEG until PARALLEL_MP init in ramstage. Was it the case that WB has some properties we want to avoid, while WC does not?