[coreboot-gerrit] Change in coreboot[master]: AGESA, binaryPI: implement C bootblock

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )

Change subject: AGESA, binaryPI: implement C bootblock
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Patch Set 30:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
File src/drivers/amd/agesa/bootblock.c:

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
PS28, Line 40: 	set_var_mtrr(mtrr, OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
> The magic value should be in %edi, not %edx? It is to make CPU really respond to the rdmsr/wrmsr ins […]

Maybe %edx, I'm a noob when it comes to clobbers...

I have researched the AMD CPU architecture and cannot come with any idea how to differentiate between cores in computing units in given node. I also don't think it will be safe to rely on initial apic ids and just program MTRR on the even apic ids (assuming BSP is always 0, so taking odd ids is a no go). Ideas?