[coreboot-gerrit] Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Angel Pons, Alexander Couzens, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 )

Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
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Patch Set 1:

(1 comment)

File src/cpu/intel/socket_p/Kconfig:

https://review.coreboot.org/c/coreboot/+/52942/comment/d46ed975_d0e98209 
PS1, Line 16: 	default 0x10000
Hmmm, we should never have added that `select NO_CBFS_MCACHE`.
> The lowest bound for L2 cache size on Socket P is 512 KiB: https://www.cpu-world.com/CPUs/Celeron_Dual-Core/Intel-Mobile%20Celeron%20Du...

Heh, ark doesn't know this SKU. For a moment I confused it
with the Core Solo (Yonah).

I have no idea what the requirements for this version of CAR
are. AFAIR, we avoided eviction by not loading too much, but
how much is that?