[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOC

[Richard Spiegel (Code Review)]

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33624 )

Change subject: soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOC
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/33624/9/src/soc/amd/stoneyridge/chi... 
File src/soc/amd/stoneyridge/chip.h:

https://review.coreboot.org/c/coreboot/+/33624/9/src/soc/amd/stoneyridge/chi... 
PS9, Line 29: MAX_DIMMS_PER_CH
> I will contact you offline

You are correct, there's some confusion on the BKDG talking about 4 DIMM, but when you get the details it's really 2 DIMM per channel making a total of 4 DIMM. Will fix.